Conventional electronic systems may include one or more memory devices such as a dynamic random access memory (DRAM), static random access memory (SRAM), Flash memory, or other conventional memory devices. A memory device stores data in vast arrays of memory cells. Each cell conventionally stores a single bit of data (a logical “1” or a logical “0”) and can be accessed or addressed. Data is output from a memory cell during a “data read” operation, and data is stored into a memory cell during a “data write” operation.
FIG. 1 illustrates a portion of a memory device 100, such as a DRAM device. Memory device 100 includes a plurality of dynamic memory cells 112, a plurality of access lines, such as word lines 114 and a plurality of data lines, such as bit lines 116. For convenience purposes, only two memory cells 112, two word lines 114 and two bit lines 116 are illustrated in FIG. 1. Memory cells 112 are organized as an array of columns and rows. Each column typically includes numerous memory cell pairs, such as the single pair illustrated in FIG. 1. Each memory cell 112 comprises a storage cell 120 (e.g., a capacitor) and an access device 122, such as a metal oxide semiconductor field effect transistor (MOSFET).
Two supply voltages are usually required to operate and access a memory cell 112. The first supply voltage is conventionally a reference voltage, such as ground and the second supply voltage is conventionally referred to as Vcc. A first cell plate of the storage cell 120 is connected to a reference voltage Vref_dvc2 having a potential between Vcc and ground. Reference voltage Vref_dvc2 is produced by a power generator 200 (see FIG. 2) and is typically equal to Vcc/2, or the average of the first and second memory cell supply voltages. The first cell plate of each storage cell 120 is typically connected to reference voltage Vref_dvc2. A second cell plate of each storage cell 120 is connected to one active terminal of an access device 122.
One of the bit lines 116 is connected to the other active terminal of the access device 122. The control terminal (e.g., gate) of the access device 122 is connected to one of the word lines 114. Thus, each memory cell 112 is connected to a word line 114 and a bit line 116. The word lines 114 and bit lines 116 form a two-dimensional array having a plurality of intersections. A single memory cell 112 corresponds to each intersection. At an intersection, word line 114 is used to selectively activate the corresponding memory cell 112. Activating the memory cell 112 connects its storage cell 120 to the corresponding bit line 116, which allows conventional memory access operations (e.g., data read, data write, and refresh) to occur.
Memory device 100 may also include an equilibrate circuit 130. The equilibrate circuit 130 may include two MOSFET transistors 132, 134. One active terminal of each transistor 132, 134 is connected to receive reference voltage Vref_dvc2. The other active terminal of each transistor 132, 134 is connected to one of the adjacent bit lines 116. The equilibrate circuit 130 is responsive to an equilibrate signal EQ to simultaneously connect reference voltage Vref_dvc2 to the bit lines 116. During normal memory access operations, the equilibrate signal EQ is activated to set the bit lines 116 to reference voltage Vref_dvc2 prior to activating the corresponding access device 122 and accessing the memory cells 112. Conventionally, the first cell plate of each storage cell 120 is maintained at reference voltage Vref_dvc2. The second cell plate of each storage cell 120 is charged to either the first memory cell supply voltage or the second memory cell supply voltage, depending on whether a “0” or “1” is being written to the storage cell 120. Data is read from the memory cells 112 of memory device 100 by activating a word line 114 (via a row decoder), which couples all of the memory cells 112 corresponding to that word line 114 to respective bit lines 116, which define the columns of the array. When a particular word line 114 is activated, sense amplifier circuitry connected to a bit line 116 detects and amplifies the data bit transferred from the storage cell 120 to its bit line 116 by measuring the potential difference between the activated bit line 116 and a reference bit line which is charged to reference voltage Vref_dvc2.
FIG. 2 illustrates a conventional power generator 200. Power generator 200 includes a first operational amplifier 202, a second operational amplifier 204, and an output reference voltage Vref_dvc2. Input reference voltage Ref_High, having a fixed magnitude, is coupled to a non-inverting input of first operational amplifier 202 and input reference voltage Ref_Low, also having a fixed magnitude, is coupled to an inverting input of second operational amplifier 204. Output reference voltage Vref_dvc2 is fed back into an inverting input of first operational amplifier 202 and a non-inverting input of second operational amplifier 204. With this feedback configuration, as output reference voltage Vref_dvc2 decreases and becomes equal to input reference voltage Ref_Low, first operational amplifier 202 supplies an active pull-up and, therefore, increases the voltage of output reference voltage Vref_dvc2. On the other hand, as output reference voltage Vref_dvc2 increases and becomes equal to input reference voltage Ref_High, second operational amplifier 204 supplies an active pull-down and, therefore, decreases the voltage of output reference voltage Vref_dvc2. As a result, this configuration ensures that output reference voltage Vref_dvc2 does not rise above input reference voltage Ref_High or fall below input reference voltage Ref_Low.
The voltage range wherein first operational amplifier 202 will not supply an active pull-up and second operational amplifier 204 will not supply an active pull-down is commonly referred to as the “dead band” (which is sometimes referred to as “hysteresis”) of power generator 200. As such, the dead band is a voltage range between input reference voltages Ref_High and input reference voltages Ref_Low and the magnitude of the dead band is determined by the values of input reference voltages Ref_High and Ref_Low. The dead band for power generators within a conventional memory device is in the range of 5 mV-200 mV.
Since memory data read/data write operations use Vref_dvc2 as a reference voltage, the magnitude and stability of output reference voltage Vref_dvc2 is very important for correct memory operation. During various operational modes, small variations in output reference voltage Vref_dvc2 can dramatically alter the functionality of a memory device. Therefore, it is desirable to have a responsive power generator with a narrow dead band. On the other hand, narrowing the dead band of a power generator for tighter control of output reference voltage Vref_dvc2 increases the frequency of active pull-ups and active pull-downs performed by the power generator. Consequently, this increases the current consumption of the power generator, which is undesirable.
There is a need for methods, devices, and systems to enhance the operation of a power generator at a relatively low power consumption. Specifically, there is a need for a power generator system including a power generator configured to operate at a variable dead band.